Key Impediments to DFT-Focused Test and How to Overcome Them

In a carefully structured study spanning several months, the authors visited numerous companies focused on Design For Test methodologies in SoC Test, Characterization, and Failure Analysis. In interviews with the leading engineers in these projects, the various DFT structures and test processes used were studied. The results of the study revealed a number of impediments to the adoption of these processes on low-cost, DFTfocused testers. This paper presents some of the more glaring difficulties together with suggestions as to how they might be overcome. Introduction Existing functional testers are expensive, and therefore, time on these machines is also expensive. The cost to test a part is the same, whether or not the cost-sensitive resources are used. For this reason, many companies have expressed an interest in using testers designed to focus on DFT test methods such as DC and AC Scan, Iddq, and BIST. Since these machines can cost as much as an order of magnitude (or more) less than a traditional tester, moving tests from the more expensive environment to the less expensive environment can save significant amounts of money. This all makes a lot of sense, of course; but is it possible to move tests from the more expensive machines to the less expensive systems? The answer lies in the manner in which the DFT structures were implemented in the devices to be tested. In this document, the authors will look at Scan and BIST techniques and point out some traps that are easy to fall into. What Costs So Much Before going into the details of the designs, it is important to understand what drives up the cost of test on traditional test equipment. Basically there are three, more or less interrelated characteristics that represent the difference between expensive and low-cost test equipment. These characteristics are: 1. Speed – the rate at which vectors can be applied. In general, the cost of increasing the vector application rate goes up exponentially with the frequency. 2. Precision – both voltage and time. As with vector rates, an increase in the precision in both time and voltage typically will cause an exponential increase in the cost of the equipment. 3. Flexibility – this is a more abstract concept, but in this context it is meant to represent such things as the number of independent complex waveform generators available, the number of tester pins available, etc. While it is more difficult to define a “flexibility variable” that relates cost to system features, it is clear that the cost of test equipment increases significantly with flexibility. So, when facing the need to reduce the cost of test equipment, DFT-focused testers are usually designed to be slower, less precise, and less flexible than their traditional cousins. This does not mean that they are less capable, however. Because DFT chip architectures focus on low-cost test techniques, the requirements for speed, precision, and flexibility have been largely removed. As a result, high-quality can be achieved without the need for expensive test equipment. The Study Over the last few months, the authors have studied Design For Test practices at a number of wellknown companies[5][6]. This study revealed that many of today’s DFT architectures are designed specifically for execution on traditional testers and as a result have grown dependent on some of the ITC INTERNATIONAL TEST CONFERENCE Paper 20.1 503 0-7803-8106-8/03 $17.00 Copyright 2003 IEEE high-cost resources that DFT-Focused machines seek to eliminate. While this may be somewhat expected (after all, DFT_Focused Test is fairly new), it is still instructive to examine some of these chip architectures, to understand the reasons for their dependence on high-cost equipment, and see what can be done to eliminate these dependencies. Memory BIST The study revealed that memory BIST is pervasive. The number and size of memories in SoCs is increasing, and MBIST is used to test virtually all except the very small. The study also revealed that most MBIST is home-grown, though there is an increasing propensity toward purchasing the technology from third parties. Homegrown solutions were preferred, in most cases where flexibility with respect to choice of algorithms was desired, and also because MBIST controllers were considered simple to design. Third party solutions were usually preferred for more sophisticated debugging mechanisms. About half of the MBIST systems that we looked at were controlled by the IEEE 1149.1 Test Access Port (TAP); the rest were controlled by a variety of mechanisms including multiplexed I/O and dedicated Internal Scan chains.[5,6,9,10] In all cases, the memories were tested at-speed; most through the use of the system clock, though a few were tested by a direct clock from the tester. There are two purposes of MBIST architectures; the first is to determine whether or not a given memory is good or bad (pass/fail) and the second is to provide information as to the exact location of the failure and the test that was running when the failure occurred (i.e. a memory map). This data can be used for two purposes; repair and process control. From this it can be seen that it is important to be able to both send data to the MBIST controller (for such things as selecting the test routine, initializing certain masks, etc.) and to receive data from the MBIST controller (for such things as pass/fail, the memory locations of failures, etc.)[9]. Many memory test engines are designed to synchronize to a single clock, and therefore they take data in and send data out, and run the test all at the same clock rate. Unfortunately, DFT-focused testers typically cannot send and receive data nearly as fast as the required clock rates of an MBIST engine (typically